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spread spectrum system frequency synthesize r w158 rev 1.0, november 21, 2006 page 1 of 12 2200 laurelwood road, santa clara, ca 95054 tel:(4 08) 855-0555 fax:(408) 855-05 50 www.spectralinear.com 1w158 features ? maximized emi suppression using cypress?s spread spectrum technology ? intel? ck98 specification compliant ? 0.5% downspread outputs deliver up to 10 db lower emi ? four skew-controlled copies of cpu output ? eight copies of pci output (synchronous w/cpu output) ? four copies of 66 mhz fixed frequency 3.3v clock ? two copies of cpu/2 outputs for synchronous memory reference ? three copies of 16.67 mhz ioapic clock, synchronous to cpu clock ? one copy of 48 mhz usb output ? two copies of 14.31818 mhz reference clock ? programmable to 133- or 100-mhz operation ? power management control pins for clock stop and shut down ? available in 56-pin ssop key specifications supply voltages: ...................................... v ddq3 = 3.3v5% ............................................................................................... v ddq2 = 2.5v5% cpu output jitter: . .............. ........... ............ ................ 150 ps cpudiv2, ioapic output jitter : ............ .............. ........ 250 ps 48 mhz, 3v66, pci output jitt er: ................ ................ 500 ps cpu0:3, cpudiv2_ 0:1 output skew: ............ ............. 175 ps pci_f, pci1:7 output skew: ... .............. .............. ........ 500 ps 3v66_0:3, ioapic0:2 output skew: ........ .............. ..... 250 ps cpu to 3v66 output offset: ....... .... 0.0 to1.5 ns (cpu leads) 3v66 to pci output offset:.......... 1.5 to 3.0 ns (3v66 leads) cpu to ioapic output offset: ...... 1.5 to 4.0 ns (cpu leads) cpu to pci output offset:............. 1.5 to 4.0 ns (cpu leads) logic inputs, except sel133/100#, have 250-k pull-up resistors table 1. pin selectable frequency [1] sel133/100# cpu0:3 (mhz) pci 1 133 mhz 33.3 mhz 0 100 mhz 33.3 mhz note: 1. see table 2 for complete mode selection details. block diagram pin configuration ref0:1 cpu0:3 cpudiv2_0:1 3v66_0:3 xtal pll 1 spread# x2 x1 pci_f pci1:7 ioapic0:2 48mhz pll2 osc 2 stop logic power three-state logic sel0 sel1 sel133/100# clock cpu_stop# 2/1.5 stop logic clock down logic 2 stop logic clock 2 2 4 2 4 1 7 3 1 pci_stop# pwrdwn# gnd ref0 ref1 vddq3 x1 x2 gnd pci_f pci1 vddq3 pci2 pci3 gnd pci4 pci5 vddq3 pci6 pci7 gnd gnd 3v66_0 3v66_1 vddq3 gnd w158 vddq2 ioapic2 ioapic1 ioapic0 gnd vddq2 cpudiv2_1 cpudiv2_0 gnd vddq2 cpu3 cpu2 gnd vddq2 cpu1 cpu0 gnd vddq3 gnd pci_stop# cpu_stop# pwrdwn# spread# sel1 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 32 31 30 29 3v66_2 3v66_3 vddq3 sel133/100# sel0 vddq3 48mhz gnd
w158 rev 1.0, november 21, 2006 page 2 of 12 overview the w158 is designed to provide the essential frequency sources to work with advanced multiprocessing intel archi- tecture platforms. split voltage supply signaling provides 2.5v and 3.3v clock frequencies operating up to 133 mhz. from a low-cost 14.31818-mhz reference crystal oscillator, the w158 generates 2.5v clock outputs to support cpus, core logic chip set, and direct rdram clock generators. it also provides skew-controlled pci and ioapic clocks synchronous to cpu clock, 48-mhz universal serial bus (usb) clock, and replicates the 14.31818-mhz reference clock. all cpu, pci, and ioapic clocks can be synchronously modulated for spread spectrum operations. cypress employs proprietary techniques that provide the maximum emi reduction while minimizing the clock skews that could reduce system timing margins. spr ead spectrum modulation is enabled by the active low control signal spread#. the w158 also includes power management control inputs. by using these inputs, system l ogic can stop cpu and/or pci clocks or power down the entire device to conserve system power. pin definitions pin name pin no. pin type pin description cpu0:3 41, 42, 45, 46 o cpu clock outputs 0 through 3: these four cpu clocks ru n at a frequency set by sel133/100#. output voltage swing is set by the voltage applied to vddq2. cpudiv2_ 0:1 49, 50 o synchronous memory reference clock output 0 through 1: reference clock for direct rdram clock generators running at 1/2 cpu clock frequency. output voltage swing is set by the voltage applied to vddq2. pci1:7 9, 11, 12, 14, 15, 17, 18 o pci clock outputs 1 through 7: these seven pci clock outputs run synchronously to the cpu clock. voltage swing is set by the power connection to vddq3. pci1:7 outputs are stopped when pci _stop# is held low. pci_f 8 o pci_f (pci free-running): this pci clock output runs syn chronously to the cpu clock. voltage swing is set by the power connection to vddq3. pci_f is not affected by the state of pci_stop#. ref0:1 2, 3 o 14.318-mhz reference clock output: 3.3v copies of the 14 .318-mhz reference clock. ioapic0:2 53, 54, 55 o i/o apic clock output: provides 16.67-mhz fixed frequency. the output voltage swing is set by the power connection to vddq2. 48mhz 30 o 48-mhz output: fixed 48-mhz usb output. output voltage swing is controlled by voltage applied to vddq3. 3v66_0:3 21, 22, 25, 26 o 66-mhz output 0 through 3: fixed 66-mhz outputs. output voltage swing is controlled by voltage applied to vddq3. sel0:1 32, 33 i mode select input 0 through 1: 3.3v lvttl-compatible input for selecting clock output modes. sel133/100# 28 i frequency selection input: 3.3v lvttl-compatible input that selects cpu output frequency as shown in table 1 . x1 5 i crystal connection or external reference frequency input: connect to either a 14.318-mhz crystal or an external reference signal. x2 6 o crystal connection: an output connection for an external 14.318-mhz crystal. if using an external reference, this pin must be left unconnected. spread# 34 i active low spread spectrum enable: 3.3v lvttl-compatible input that enables spread spectrum mode when held low. pwrdwn# 35 i active low power down input: 3.3v lvttl-compatible asynchronous input that requests the device to enter power-down mode. cpu_stop# 36 i active low cpu clock stop: 3.3v lvttl-compatible asynch ronous input that stops all cpu and 3v66 clocks when held low. cpud iv2 outputs are unaffected by this input. pci_stop# 37 i active low pci clock stop: 3.3v lvttl-compatible asynch ronous input that stops all pci outputs except pci_f when held low. vddq3 4, 10, 16, 23, 27, 31, 39 p power connection: power supply for pci output buffers, 48-mhz usb output buffer, reference output buffers, 3v66 output buffers , core logic, and pll circuitry. connect to 3.3v supply. vddq2 43, 47, 51, 56 p power connection: power supply for ioapic, cpu, and cpudiv2 output buffers. connect to 2.5v supply. gnd 1, 7, 13, 19, 20, 24, 29, 38, 40, 44, 48, 52 g ground connection: connect all ground pins to the common system ground plane.
w158 rev 1.0, november 21, 2006 page 3 of 12 spread spectrum clocking the device generates a clock that is frequency modulated in order to increase the bandwidth t hat it occupies. by increasing the bandwidth of the fundamental and its harmonics, the ampli- tudes of the radiated electrom agnetic emissions are reduced. this effect is depicted in figure 1 . as shown in figure 1 , a harmonic of a modulated clock has a much lower amplitude than that of an unmodulated signal. the reduction in amplitude is dependent on the harmonic number and the frequency deviation or spread. the equation for the reduction is: db = 6.5 + 9*log 10 (p) + 9*log 10 (f) where p is the percentage of deviation and f is the frequency in mhz where the reduction is measured. the output clock is modulated with a waveform depicted in figure 2 . this waveform, as discussed in ?spread spectrum clock generation for the reduct ion of radiated emissions? by bush, fessler, and hardin produces the maximum reduction in the amplitude of radiated electromagnetic emissions. the deviation selected for this chip is ?0.5% downspread. figure 2 details the cypress spreading pattern. cypress does offer options with more spread and gr eater emi reduction. contact your local sales representative for details on these devices. figure 1. clock harmonic with and without sscg modulation frequency domain representation 100% 60% 20% 80% 40% 0% ?20% ?40% ?60% ?80% ?100% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% time frequency shift figure 2. modulation waveform profile
w158 rev 1.0, november 21, 2006 page 4 of 12 mode selection functions the w158 supports the following operating modes contro lled through the sel133/100#, sel0, and sel1 inputs. notes: 2. provided for board level ?bed of nails? testing. 3. 48-mhz pll disabled to reduce component jitter. 4. normal? mode of operation. 5. tclk is a test clock over driven on the x1 input during test mode. tclk mode is based on 133-mhz cpu select logic. 6. required for dc output impedance verification. 7. range of reference frequency is min.=14.316, nominal = 14.31818 mhz, max.=14.32 mhz. 8. frequency accuracy of 48 mhz is +167 ppm to match usb default. table 2. select functions sel133/100# sel1 sel0 function 0 0 0 all outputs three-state 0 0 1 (reserved) 0 1 0 active 100-mhz, 48-mhz pll inactive 0 1 1 active 100-mhz, 48-mhz pll active 1 0 0 test mode 1 0 1 (reserved) 1 1 0 active 133-mhz, 48-mhz pll inactive 1 1 1 active 133-mhz, 48-mhz pll active table 3. truth table sel 133/100# sel1 sel0 cpu cpudiv2 3v6 6 pci 48mhz ref ioapic notes 0 0 0 hi-z hi-z hi-z hi-z hi-z hi-z hi-z 2 0 0 1 n/a n/a n/a n/a n/a n/a n/a 0 1 0 100 mhz 50 mhz 66 mhz 33 mhz hi-z 14.318 mhz 16.67 mhz 3 0 1 1 100 mhz 50 mhz 66 mhz 33 mhz 48 mhz 14.318 mhz 16.67 mhz 4, 7, 8 1 0 0 tclk/2 tclk/4 tclk/4 tclk/8 tclk/2 tclk tclk16 5, 6 1 0 1 n/a n/a n/a n/a n/a n/a n/a 1 1 0 133 mhz 66 mhz 66 mhz 33 mhz hi-z 14.318 mhz 16.67 mhz 3 1 1 1 133 mhz 66 mhz 66 mhz 33 mhz 48 mhz 14.318 mhz 16.67 mhz 4, 7, 8 table 4. maximum supply current condition max. 2.5v supply consumption max. discrete cap loads, v ddq2 =2.625v all static inputs=v ddq3 or gnd max. 3.3v supply consumption max. discrete cap loads, v ddq3 =3.465v or gnd powerdown mode (pwrdwn#=0) 100 a 200 a full active 100 mhz sel133/100#=0 sel1, 0=11 cpu_stop#, pci_stop#=1 75 ma 160 ma full active 133 mhz sel133/100#=0 sel1, 0=11 cpu_stop#, pci_stop#=1 90 ma 160 ma
w158 rev 1.0, november 21, 2006 page 5 of 12 table 5. clock enable configuration [9, 10, 11, 12, 13, 14] cpu_stop# pwrdwn# pci_stop# cpu cpudiv2 ioapic 3v66 pci pci_f ref, 48mhz osc. vcos x 0 x low low low low low low low off off 0 1 0 low on on low low on on on on 0 1 1 low on on low on on on on on 1 1 0 on on on on low on on on on 1 1 1 on on ononononononon table 6. power management state transition [15, 16] signal signal state latency no. of rising edges of pci clock cpu_stop# 0 (disabled) 1 1 (enabled) 1 pci_stop# 0 (disabled) 1 1 (enabled) 1 pwrdwn# 1 (normal operation) 3 ms 0 (power down) 2 max. timing diagrams cpu_stop# timing diagram [17, 18, 19, 20, 21, 22] notes: 9. low means outputs held static low as per latency requirement below. 10. on means active. 11. pwrdwn# pulled low, impacts all outputs including ref and 48-mhz outputs. 12. all 3v66 as well as all cpu clocks stop cleanly when cpu_stop# is pulled low. 13. cpudiv2, ioapic, ref, 48mhz signals are not controlled by the cpu_stop# functionality and are enabled in all conditions exce pt pwrdwn#=low. 14. an ?x? indicates a ?don?t care? condition. 15. clock on/off latency is defined in the number of rising edges of the free-running pci clock between when the clock disable g oes low/high to when the first valid clock comes out of the device. 16. power up latency is from when pwrdwn# goes inactive (high) to when the first valid clocks are driven from the device. 17. all internal timing is referenced to the cpu clock. 18. the internal label means inside the chip and is a reference only. this, in fact, may not be the way that the control is desi gned. 19. cpu_stop# signal is an input signal that must be made synchronous to free-running pci_f. 20. 3v66 clocks also stop/start before. 21. pwrdwn# and pci_stop# are shown in a high state. 22. diagrams shown with respect to 133 mhz. similar operation when cpu clock is 100 mhz. cpu pci cpu_stop# pci_stop# pwrdwn# 3v66 (internal) hi hi cpu (external)
w158 rev 1.0, november 21, 2006 page 6 of 12 pci_stop# timing diagram [18, 22, 23, 24, 25, 26] pwrdwn# timing diagram [18, 22, 23, 27, 28] notes: 23. all internal timing is referenced to the cpu clock. 24. pci_stop# signal is an input signal th at must be made synchronous to pci_f output. 25. all other clocks continue to run undisturbed. 26. pwrdwn# and cpu_stop# are shown in a high state. 27. pwrdwn is an asynchronous input and metastable c onditions could exist. this signal must be synchronized. 28. the shaded sections on the vco and the crystal signals indicate an active clock. timing diagrams (continued) cpu pci pci_stop# pwrdwn# pci_f (external) hi hi (internal) pci (external) cpu_stop# cpu pci pwrdwn# vco crystal pci cpu (internal) (internal) (external) (external)
w158 rev 1.0, november 21, 2006 page 7 of 12 absolute maximum ratings [29] stresses greater than those listed in this table may cause permanent damage to the devic e. these represent a stress rating only. operation of the devi ce at these or any other condi- tions above those specified in the operating sections of this specification is not implied. maximum conditions for extended periods may affect reliability. . parameter descrip tion rating unit v dd , v in voltage on any pin with respect to gnd ?0.5 to +7.0 v t stg storage temperature ?65 to +150 c t a operating temperature 0 to +70 c t b ambient temperature under bias ?55 to +125 c esd prot input esd protection 2 (min.) kv dc electrical characteristics: t a = 0c to +70c, v ddq3 = 3.3v5%, v ddq2 = 2.5v5% parameter description test condition min. typ. max. unit supply current i dd-3.3v combined 3.3v supply current cpu0:3 =133 mhz [30] 160 ma i dd-2.5 combined 2.5v supply current cpu0:3 =133 mhz [30] 90 ma logic inputs (all referenced to v ddq3 = 3.3v) v il input low voltage gnd ?0.3 0.8 v v ih input high voltage 2.0 vdd+ 0.3 v i il input low current [31] ?25 a i ih input high current [31] 10 a i il input low current, sel133/100# [31] ?5 a i ih input high current, sel133/100# [31] 5a clock outputs cpu, cpudiv2, ioapic (referenced to v ddq2 ) test condition min. typ. max. unit v ol output low voltage i ol = 1 ma 50 mv v oh output high voltage i oh = ?1 ma 2.2 v i ol output low current v ol = 1.25v 45 65 100 ma i oh output high current v oh = 1.25v 45 65 100 ma 48mhz, ref (referenced to v ddq3 ) test condition min. typ. max. unit v ol output low voltage i ol = 1 ma 50 mv v oh output high voltage i oh = ?1 ma 3.1 v i ol output low current v ol = 1.5v 45 65 100 ma i oh output high current v oh = 1.5v 45 65 100 ma pci, 3v66 (referenced to v ddq3 ) test condition min. typ. max. unit v ol output low voltage i ol = 1 ma 50 mv v oh output high voltage i oh = ?1 ma 3.1 v i ol output low current v ol = 1.5v 70 100 145 ma i oh output high current v oh = 1.5v 65 95 135 ma notes: 29. multiple supplies: the voltage on any input or i/o pin cannot exceed the power pin during power-up. power supply sequencing is not required. 30. all clock outputs loaded with 6" 60 transmission lines with 20-pf capacitors. 31. w158 logic inputs have internal pull-up devices, except sel133/100# (pull-ups not cmos level).
w158 rev 1.0, november 21, 2006 page 8 of 12 3.3v ac electrical characteristics t a = 0c to +70c, v ddq3 = 3.3v5%, v ddq2 = 2.5v 5%, f xtl = 14.31818 mhz spread spectrum function turned off ac clock parameters are tested and guarant eed over stated operating conditions using the stated lump capacitive load at the clock output. [35] notes: 32. x1 input threshold voltage (typical) is v dd /2. 33. the w158 contains an internal crystal load capacitor between pin x1 and ground and another between pin x2 and ground. total load placed on crystal is 18 pf; this includes typical stray capacitance of short pcb traces to crystal. 34. x1 input capacitance is a pplicable when driving x1 wit h an external clock source (x2 is left unconnected). 35. period, jitter, offset, and skew measured on rising edge at 1.5v. 36. 3v66 is cpu/2 for cpu =133 mhz and (2 x cpu)/3 for cpu = 100 mhz. crystal oscillator v th x1 input threshold voltage [32] 1.65 v c load load capacitance, imposed on external crystal [33] 18 pf c in,x1 x1 input capacitance [34] pin x2 unconnected 28 pf pin capacitance/inductance c in input pin capacitance except x1 and x2 5 pf c out output pin capacitance 6 pf l in input pin inductance 7nh dc electrical characteristics: t a = 0c to +70c, v ddq3 = 3.3v5%, v ddq2 = 2.5v5% parameter description test condition min. typ. max. unit 3v66 clock outputs, 3v66_0:3 (lump capacitance test load = 30 pf) parameter description test condition/comments min. typ. max. unit f frequency note 36 66.6 mhz t r output rise edge rate measured from 0.4v to 2.4v 1 4 v/ns t f output fall edge rate measured from 2.4v to 0.4v 1 4 v/ns t d duty cycle measured on rising and falling edge at 1.5v 45 55 % f st frequency stabilization from power-up (cold start) assumes full supply voltage reached within 1 ms from power-up. short cycles exist prior to frequency stabilization. 3ms z o ac output impedance average val ue during switching transition. used for determining series termination value. 15
w158 rev 1.0, november 21, 2006 page 9 of 12 note: 37. pci clock is cpu/4 for cpu = 133 mhz and cpu/3 for cpu = 100 mhz. pci clock outputs, pci_f and pci1:7 (lump capacitance test load = 30 pf) parameter description test condit ion/comments min. typ. max. unit t p period measured on rising edge at 1.5v [37] 30 ns t h high time duration of clock cycle above 2.4v 12 ns t l low time duration of clock cycle below 0.4v 12 ns t r output rise edge rate measur ed from 0.4v to 2.4v 1 4 v/ns t f output fall edge rate measured from 2.4v to 0.4v 1 4 v/ns t d duty cycle measured on rising and falling edge at 1.5v 45 55 % t jc jitter, cycle-to-cycle measured on rising edge at 1.5v. maximum difference of cycle time between two adjacent cycles. 500 ps t sk output skew measured on rising edge at 1.5v 500 ps t o 3v66 to pci clock skew covers all 3v66/pci outputs. measured on rising edge at 1.5v. 3v66 leads pci output. 1.5 3 ns t q cpu to pci clock skew covers all cpu/pci outputs. measured on rising edge at 1.5v. cpu leads pci output. 1.5 4 ns f st frequency stabilization from power-up (cold start) assumes full supply voltage reached within 1 ms from power-up. short cycles exist prior to frequency stabilization. 3ms z o ac output impedance average value duri ng switching transition. used for deter- mining series termination value. 15 ref clock outputs, ref0:1 (lump capacitance test load = 20 pf) parameter description test condition/comments min. typ. max. unit f frequency, actual frequency generated by crystal oscillator 14.318 mhz t r output rise edge rate measured from 0.4v to 2.4v 0.5 2 v/ns t f output fall edge rate measured from 2.4v to 0.4v 0.5 2 v/ns t d duty cycle measured on rising and falling edge at 1.5v 45 55 % f st frequency stabilization from power-up (cold start) assumes full supply voltage reached within 1 ms from power-up. short cycles exist prior to frequency stabilization. 3ms z o ac output impedance average value du ring switching transition. used for determining series termination value. 25 48-mhz clock output (lump capacitance test load = 20 pf) parameter description test condition/comments min. typ. max. unit f frequency, actual determined by pll divider ratio (see m/n below) 48.008 mhz f d deviation from 48 mhz (48.008 ? 48)/48 +167 ppm m/n pll ratio (14.31818 mhz x 57/17 = 48.008 mhz) 57/17 t r output rise edge rate measured from 0.4v to 2.4v 0.5 2 v/ns t f output fall edge rate measured from 2.4v to 0.4v 0.5 2 v/ns t d duty cycle measured on rising and falling edge at 1.5v 45 55 % f st frequency stabilization from power-up (cold start) assumes full supply voltage reached within 1 ms from power-up. short cycles exist prior to frequency stabilization. 3ms z o ac output impedance average value during switching transition. used for determining series termination value. 25
w158 rev 1.0, november 21, 2006 page 10 of 12 2.5v ac electrical characteristics t a = 0c to +70c, v ddq3 = 3.3v5%, v ddq2 = 2.5v5% f xtl = 14.31818 mhz spread spectrum function turned off ac clock parameters are tested and guarant eed over stated operating conditions using the stated lump capacitive load at the clock output. [38] note: 38. period, jitter, offset, and skew measured on rising edge at 1.25v. cpu clock outputs, cpu0:3 (lump capacitance test load = 20 pf) parameter description test condition/comments cpu = 133 mhz cpu = 100 mhz unit min. typ. max. min. typ. max. t p period measured on rising edge at 1.25v 7.5 7.65 10 10.2 ns t h high time duration of clock cycle above 2.0v 1.87 3.0 ns t l low time duration of clock cycle below 0.4v 1.67 2.8 ns t r output rise edge rate measured from 0.4v to 2.0v 1 4 1 4 v/ns t f output fall edge rate measured from 2.0v to 0.4v 1 4 1 4 v/ns t d duty cycle measured on rising and falling edge at 1.25v 45 55 45 55 % t jc jitter, cycle-to-cycle measured on rising edge at 1.25v. maximum difference of cycle time between two adjacent cycles. 150 150 ps t sk output skew measured on ri sing edge at 1.25v 175 175 ps f st frequency stabili- zation from power-up (cold start) assumes full supply voltage reached within 1 ms from power-up. short cycles exist prior to frequency stabilization. 33ms z o ac output impedance average value during switching transition. used for determining series termination value. 20 20 cpudiv2 clock outputs, cpudiv2_0:1 (lump capacitance test load = 20 pf) parameter description test condition/comments cpu = 133 mhz cpu = 100 mhz unit min. typ. max. min. typ. max. t p period measured on rising edge at 1.25v 15 15.3 20 20.4 ns t h high time duration of clock cycle above 2.0v 5.25 7.5 ns t l low time duration of clock cycle below 0.4v 5.05 7.3 ns t r output rise edge rate measured from 0.4v to 2.0v 1 4 1 4 v/ns t f output fall edge rate measured from 2.0v to 0.4v 1 4 1 4 v/ns t d duty cycle measured on rising and falling edge at 1.25v 45 55 45 55 % t jc jitter, cycle-to-cycle measured on rising edge at 1.25v. maximum difference of cycle time between two adjacent cycles. 250 250 ps t sk output skew measured on ri sing edge at 1.25v 175 175 ps f st frequency stabili- zation from power-up (cold start) assumes full supply voltage reached within 1 ms from power-up. short cycles exist prior to frequency stabilization. 33ms z o ac output impedance average value during switching transition. used for determining series termination value. 20 20
w158 rev 1.0, november 21, 2006 page 11 of 12 note: 39. ioapic clock is cpu/8 for cpu = 133 mhz and cpu/6 for cpu = 100 mhz. ioapic clock outputs, ioapic0:2 (lump capacitance test load = 20 pf) parameter description test cond ition/comments min typ max unit f frequency note 39 16.67 mhz t r output rise edge rate measured from 0.4v to 2.0v 1 4 v/ns t f output fall edge rate measured from 2.0v to 0.4v 1 4 v/ns t d duty cycle measured on rising and falling edge at 1.25v 45 55 % f st frequency stabilization from power-up (cold start) assumes full supply voltage reached within 1 ms from power-up. short cycles exist prior to frequency stabilization. 3ms z o ac output impedance average value du ring switching transition. used for determining series termination value. 20
rev 1.0, november 21, 2006 page 12 of 12 w158 while sli has reviewed all information herein for accuracy and re liability, spectra linear inc. assumes no responsibility for t he use of any cir- cuitry or for the infringement of any patents or other rights of third parties which would result from each use. this product i s intended for use in normal commercial applications and is not warranted nor is it inte nded for use in life support, critical medical instruments, o r any other applica- tion requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursu ant to additional processing by spectra linear in c., and expressed written agreement by spectra linear inc. spectra linear inc. reserves the righ t to change any circuitry or specification without notice. ordering information ordering code package name package type w158 h 56-pin ssop (300 mils) package diagram 56-lead shrunk small outline package o56

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